1. Field of Invention
This invention relates in general to current switch logic and, in particular, to current switch logic in which a pair of bistable devices are cascoded to provide a shift register latch pair for level sensitive scan design testing.
2Description of the Prior Art
Very Large Scale Integration (VLSI) technology has increased the number of transistor devices that may be placed on semiconductor chips. As the number of devices increases and, hence, the number of possible circuits increases, two areas of concern have developed. The amount of power that is consumed by the chip becomes a problem in that power consumed is converted to heat which must be dissipated and controlled if the chip is to operate satisfactorily. It is known in the art that power can be reduced by employing a multi-level Cascode Current Switch (CCS) technology such as disclosed in U.S. Pat. No. 3,446,989. In CCS logic, a basic logic tree involves a number of levels each comprising basic cells. In one known arrangement, referred to as Cascode Emitter Coupled Logic (CECL), a basic cell comprises a pair of bipolar type transistors which have their emitters coupled together to either a current source for the tree or to an output of the cell in the preceding level. The cell includes two output terminals and three control input terminals comprising the bases of the respective transistors in the cell and the common emitter terminal. If the control input terminals are supplied with the true and complement form of the logic input signal, the system is referred to as a Differential CCS (DCCS) or double-rail type system. In some implementations, one control input is supplied with a reference signal, while the other input terminal receives the true form of the logic signal. The two output terminals are connected to different cells in the next higher level of the tree.
The number of levels selected for the tree can vary from two up to six, seven or eight, depending on the complexity of the logic desired to be accomplished. The output of the tree is connected to a voltage source through load resistors, while the first level of the tree has its input connected to a current source. Only one current path may be established between the current source and the load resistor since, at each level, the current from the preceding level is supplied or steered to only one cell at that level and, in turn, the cell output steers current to only one cell at the next level. Logically, "N" cascoded cells may represent an "N" input AND-gate or a complex logic function in that selected current switches at each level are connected in series. The logical arrangement is similar in many respects to relay logic employed in early data processing machines.
The other concern which arises as the number of circuits increases on a chip is the problem of testing the devices per se or the circuits formed from devices after the chip has had the devices connected together to give the desired function. A system is presently employed in the art which operates to test each circuit in the chip. A description of this testing technique, referred to as Level Sensitive Scan Design testing (LSSD), may be found in U.S. Pat. No. 3,783,254, 3,806,891 and IBM Technical Disclosure Bulletin, Vol. 22, No. 8B, January 1980, page 3660. The essence of such a system is to provide a linked pair of latches L1 and L2 which form a Shift Register Latch (SRL) stage. In order to implement an LSSD testing approach for cascode current logic, it has been the practice to provide a current source associated with the L1 latch and a second current source for the L2 latch of the Shift Register Latch stage. A typical prior art implementation for LSSD testing is shown in FIG. 1 of the drawing. The present invention is an improvement over the arrangement shown in FIG. 1 in that the second current source is eliminated and the L2 latch is effectively merged with the L1 latch and, hence, employs the same current source.